vhdl quick start  *    vhdl quick start  *  objective  quick introduction to vhdl  basic language concepts  basic design methodology  use the student’s guide to vhdl  or the designer’s guide to vhdl  self-learning for more depth  reference for project work  *    vhdl quick start  *  modeling digital systems  vhdl is for writing models of a system  reasons for modeling  requirements specification  documentation  testing using simulation  formal verification  synthesis  goal  
most reliable design process, with minimum cost and time
avoid design errors!
*    vhdl quick start  *  domains and levels of modeling  high level of abstraction  functional  structural  geometric  “y-chart” due to gajski & kahn  low level of abstraction  *    vhdl quick start  *  domains and levels of modeling  functional  structural  geometric  “y-chart” due to gajski & kahn  algorithm  (behavioral)  register-transfer  language  boolean equation  differential equation  *     1998, peter j.ashenden  vhdl quick start  *  domains and levels of modeling  functional  structural  geometric  “y-chart” due to gajski & kahn  processor-memory  switch  register-transfer  gate  transistor  *    vhdl quick start  *  domains and levels of modeling  functional  structural  geometric  “y-chart” due to gajski & kahn  polygons  sticks  standard cells  floor plan    vhdl quick start  *  basic vhdl concepts  interfaces  behavior  structure  test benches  analysis, elaboration, simulation  synthesis     1998, peter j.ashenden  vhdl quick start  *  modeling interfaces  entity declaration  describes the input/output ports of a module  entity reg4 is  port ( d0, d1, d2, d3, en, clk : in bit;  q0, q1, q2, q3 : out bit );  end entity reg4;  entity name  port names  port mode (direction)  port type  reserved words  punctuation     1998, peter j.ashenden  vhdl quick start  *  vhdl-87  omit entity at end of entity declaration  entity reg4 is  port ( d0, d1, d2, d3, en, clk : in bit;  q0, q1, q2, q3 : out bit );  end reg4;     1998, peter j.ashenden  vhdl quick start  *  modeling behavior  architecture body  describes an implementation of an entity  may be several per entity  behavioral architecture  
describes the algorithm performed by the module
contains  process statements, each containing  sequential statements, including  signal assignment statements and  wait statements     1998, peter j.ashenden  vhdl quick start  *  behavior example  architecture behav of reg4 is  begin  storage : process is  
variable stored d0, stored d1, stored d2, stored d3 : bit;
begin  if en 1 and clk 1 then  stored d0 : d0;  stored d1 : d1;  stored d2 : d2;  stored d3 : d3;  end if;  q0 < stored d0 after 5 ns;  q1 < stored d1 after 5 ns;  q2 < stored d2 after 5 ns;  q3 < stored d3 after 5 ns;  wait on d0, d1, d2, d3, en, clk;  end process storage;  end architecture behav;     1998, peter j.ashenden  vhdl quick start  *  vhdl-87  omit architecture at end of architecture body  omit is in process statement header  architecture behav of reg4 is  begin  storage : process  
.
begin  
.
end process storage;  end behav;     1998, peter j.ashenden  vhdl quick start  *  modeling structure  structural architecture  
implements the module as a composition of subsystems
contains  
signal declarations, for internal interconnections
the entity ports are also treated as signals  component instances  
instances of previously declared entity/architecture pairs
port maps in component instances  connect signals to component ports  wait statements     1998, peter j.ashenden  vhdl quick start  *  structure example     1998, peter j.ashenden  vhdl quick start  *  structure example  
first declare d-latch and and-gate entities and architectures
entity d latch is  port ( d, clk : in bit; q : out bit );  end entity d latch;  architecture basic of d latch is  begin  latch behavior : process is  begin  if clk ‘1’ then  q < d after 2 ns;  end if;  wait on clk, d;  end process latch behavior;  end architecture basic;  entity and2 is  port ( a, b : in bit; y : out bit );  end entity and2;  architecture basic of and2 is  begin  and2 behavior : process is  begin  y < a and b after 2 ns;  wait on a, b;  end process and2 behavior;  end architecture basic;     1998, peter j.ashenden  vhdl quick start  *  structure example  now use them to implement a register  architecture struct of reg4 is  signal int clk : bit;  begin  bit0 : entity work.d latch(basic)  port map ( d0, int clk, q0 );  bit1 : entity work.d latch(basic)  port map ( d1, int clk, q1 );  bit2 : entity work.d latch(basic)  port map ( d2, int clk, q2 );  bit3 : entity work.d latch(basic)  port map ( d3, int clk, q3 );  gate : entity work.and2(basic)  port map ( en, clk, int clk );  end architecture struct;     1998, peter j.ashenden  vhdl quick start  *  vhdl-87  
can’t directly instantiate entity/architecture pair
instead  
include component declarations in structural architecture body
templates for entity declarations  instantiate components  write a configuration declaration  
binds entity/architecture pair to each instantiated component
   1998, peter j.ashenden  vhdl quick start  *  structure example in vhdl-87  
first declare d-latch and and-gate entities and architectures
entity d latch is  port ( d, clk : in bit; q : out bit );  end d latch;  architecture basic of d latch is  begin  latch behavior : process  begin  if clk ‘1’ then  q < d after 2 ns;  end if;  wait on clk, d;  end process latch behavior;  end basic;  entity and2 is  port ( a, b : in bit; y : out bit );  end and2;  architecture basic of and2 is  begin  and2 behavior : process  begin  y < a and b after 2 ns;  wait on a, b;  end process and2 behavior;  end basic;     1998, peter j.ashenden  vhdl quick start  *  structure example in vhdl-87  
declare corresponding components in register architecture body
architecture struct of reg4 is  component d latch  port ( d, clk : in bit; q : out bit );  end component;  component and2  port ( a, b : in bit; y : out bit );  end component;  signal int clk : bit;     (이하 생략)